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ATmega128
Overview of the
TWI Module
The T W I module is comprised of several submodules, as shown in Figure 94 . All registers drawn
in a thick line are accessible through the AVR data bus.
Figure 94. Overview of the T W I Module
SCL
SDA
Slew-rate
Control
Spike
Filter
Slew-rate
Control
Spike
Filter
Bus Interface Unit
Bit Rate Generator
START / STOP
Control
Spike Suppression
Prescaler
Arbitration detection
Address Match Unit
Address/Data Shift
Register (TWDR)
Ack
Control Unit
Bit Rate Register
(TWBR)
Address Register
(TWAR)
Status Register
(TWSR)
Control Register
(TWCR)
Address Comparator
State Machine and
Status control
SCL frequency = -----------------------------------------------------------
16 + 2(T W BR) ? 4
Scl and SDA Pins
Bit Rate Generator
Unit
These pins interface the AVR T W I with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the T W I specification. The input stages contain a spike
suppression unit removing spikes shorter than 50ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the T W I Bit Rate Register (T W BR) and the Prescaler bits in the T W I Status
Register (T W SR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average T W I bus clock
period. The SCL frequency is generated according to the following equation:
CPU Clock frequency
TWPS
?
?
T W BR = Value of the T W I Bit Rate Register
T W PS = Value of the prescaler bits in the T W I Status Register
Note:
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See Table 133 on page 322 for value of pull-up resistor.
Bus Interface Unit
This unit contains the Data and Address Shift Register (T W DR), a START/STOP Controller and
Arbitration detection hardware. The T W DR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit T W DR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
203
2467X–AVR–06/11
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